Welcome to part 3 of this series!
In the last part we discusses the CPU and some of it’s basic parts which included ALU, Control Unit and Register. In this part we will connect two additional components and they are called Bus and Memory as shown on the diagram.
This is also where the Von Neumann architecture comes into play as mention in part one. As we can see on the diagram we now have the “Bus” which connects the CPU and the memory. You can think of the bus a highway. This is where all the bits flows back and forth between CPU and memory. The Register Unit located on the CPU itself is very similar to the memory module you see on the right side. They both have uniquely addressed cells. Since the Register Unit is located on the CPU chip itself it is extremely fast because it doesn’t have to leave the CPU chip to get data. I have mentioned that the data that is located in the cells of the Register Unit is used for temporary storage of data and that is because it stores data that will be used immediately. The cells located on the memory module are the ones that are likely to be used “in the near future”.
Please note that all memory cells are equal.
So let’s take another example:
Imaging that we have the number 5 placed inside of cell A7 above and number 9 placed inside the cell A2 above on the memory module and that we want to transfer these numbers to the Register Unit cell number 10 and 12.
(I choose these cell numbers and values randomly for this example – in real life it depends on the instruction)
Just keep in mind that each cell can fit one character (8 bits). That means that to store the name Rose we need four memory / register unit cells.
Step 1: The Control Unit will get what is located in A7 on the memory module (number 5) and transfer this number over the bus and place it in the Register Unit cell number 10.
Step 2: Same thing. The Control Unit will get what is located in A2 on the memory module (number 9) and transfer this number over the bus and place it in the Register Unit cell number 10.
Now you know why we get delay, because the number has to “drive” all the way from the memory module over the “highway” (the bus) and finally be placed in a cell in the Register Unit.
Good, so by now we have been able to transfer the two numbers from the memory module to the Register Unit which is located on the CPU.
Step 3: The Control Unit which is responsible for the transfer will inform the Arithmetic/Logic Unit (ALU) that is has placed number 5 in cell 10 and number 9 in cell 12 in the Register Unit as input. It will also tell the ALU that it wants to receive the result in Register Unit cell number 13.
Step 4: The Arithmetic/Logic Unit (ALU) will do the job (add number 9 to 5 which is 14 – leave the result in Register Unit cell number 13 as instructed by the Control Unit.
Step 5: The Control Unit might transfer the result back to the memory module and place it in a new cell (depending on the instruction)
This is what the CPU does over and over again. We call this the machine cycle.
Fetch > Decode > Execute. This is why we can only use the cells in the Register Unit for temporary storage because we need them for the flow of incoming instructions.
The Control Unit can either LOAD (get) or STORE (write) information to cells.
You now know basic concept of the Von Neumann architecture.
Continue to part 4 where we will see some of the challenges we have with this architecture in todays computing.
Welcome to part 3 of this series!