CPU the easy way – Part 4 (Von Neumann bottleneck)

In the last three posts in this series we have covered the Arithmetic/Logic Unit (ALU), the Control Unit, memory and bus.
So far we have seen that the Von Neumann architecture is working very well by transferring instructions and data back and forth between memory and CPU via a bus.
So what is this Von Neumann bottleneck all about?
Well, in real life we have several other components in our computer. We usually have a hard disk drive, DVD-ROM and probably a fancy graphics card that allows us to play games with good 3D graphics. These components have controllers them self that are directly connected to the bus.

Example:
When you go guy a Nvidia GeForce graphics card these days it has its own CPU and memory located on the graphics card itself. When you plug this card into your computer, it is now communicating directly with the bus. Since the card has its own memory – that means that it also has cells just as the Register Unit and the memory module. The Control Unit on the CPU now knows that cells starting with A are located in the memory module and cells starting with B is located on the graphics controller.
Since the controller is connected to the bus, it can carry on its own communication with the memory module during the times that the CPU is not “occupying” the bus.
This is what we call direct memory access (DMA). The CPU can send instructions to the graphics controller asking it to do tasks, and while the graphics controller is working on that particular task, the CPU can work on another task in the meanwhile. This is good for performance since we are able to share the work between two components.
Data must now move between CPU and the memory module, between CPU and the graphics controller and between the graphics controller and main memory. Coordination of all this activity on the bus is a major design issue since the controllers compete for bus access, especially when we keep adding things such as hard disk controller etc. This is the Von Neumann bottleneck because the bus has limited throughput and the CPU is then forced to wait.
I hope you have gained more knowledge about CPU, memory and the Von Neumann architecture in this series. There are a lot more things going on here, but with what you have learned now you can add knowledge on top of that, such as why we have a cache inside of the CPU chip. The design started out very simple in the early days, but computer scientists and companies has added layers on top, and that’s why it can be difficult to understand how the CPU works when there are so many details.
Feel free to drop a comment!